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AT45DB011B
Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
SI
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r r r r
r r XX
XXXX XXXX
XXXX XXXX
LSB
Reserved for
larger densities
Page Address
(PA8-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
Notes:
1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
15
1984J–DFLASH–06/06
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